15 credits at level HE7
This module introduces high level digital integrated circuit design techniques, design methodologies and the practical use of CAD tools to design and test complex digital circuits. The study time divides into two halves. The first half deals with the design techniques and methodologies particularly appropriate to the implementation of digital systems on silicon and is delivered in instructional web based format with accompanying self assessment questions. The second half of the study time is allocated to the implementation of a digital system on a standard cell device using the Cadence design flow. This activity is delivered online to the students from a central UNIX CAD server via a fast communications protocol that is optimised for the internet.
Who can benefit?
The module is particularly appropriate for electronic designers entering the field of digital integrated circuit design. You will have a good working knowledge of basic digital design and a requirement to learn how to re-engineer systems on silicon. Experience of relevant CAD tools is not essential as full instruction is provided. Some experience of VHDL is desirable but accompanying instructional material will be available. The module can be studied on its own or as part of a programme leading to a qualification.
The module aims to develop an awareness and understanding of:
- use of digital IC design tools and techniques
- digital design principles influencing efficiency, reliability and robustness.
- the complete digital design flow
Best Practice Digital Design
An in-depth treatment of correct design procedures for the production of reliable, robust digital systems. This section also includes a Designer's Guide providing a review of digital design techniques and methodologies.
Control Unit Design
A comprehensive consideration of the Algorithmic State Machine (ASM) method for the design of digital control units implemented by Finite State Machines (FSM).
Full Custom Design
Simple and complex gate structures, block structures (RAM, ROM, PLA), design considerations.
Design for Testability
Principles of device testing, testing techniques, design structures for enhancing testability.
Design Flow Walkthroughs
A comprehensive series of walkthroughs outlining the complete digital circuit design flow. Topics include cell library and full custom component design, schematic entry, VHDL/Verilog specification and logic synthesis, functional and gate level simulation, placement, routing and final layout.
Included is a substantial design assignment utilising the complete Cadence digital design flow and incorporating control and dataflow structures, cell library, synthesised and full custom components and IP (Intellectual Property) cores.
The module is expected to involve 150 hours learning time spread over 12 weeks. All study and assessment is carried out via the internet so there is no requirement to attend in person. The approach is substantially student centered, with tutor support by email and telephone on a one-to-one basis, although peer discussion is encouraged. Typically the generality of a concept is introduced in the online text and the student is then directed to a variety of information sources to research and analyse the subject area further, reflect and draw appropriate conclusions. Self-assessment questions (SAQs) throughout the module reinforce the concepts and help students to monitor their progress and the effectiveness of their study. The module includes practical work using remote access to industry standard software hosted centrally. The module is assessed by one substantial assignment which allows the student to demonstrate expertise in advanced professional skills in the learning outcomes identified.
when you have successfully completed this module you will:
to demonstrate that you have achieved the learning outcome you will:
|1.||be able to demonstrate awareness and understanding of digital IC design tools and techniques.||exercise appropriate judgement in a number of complex planning and design features of digital design tools.|
|2.||be able to demonstrate awareness and understanding of digital design principles such as efficiency, reliability and robustness.||transfer and apply diagnostic and creative skills to develop the criteria for maintaining efficiency, reliability and robustness.|
|3.||be able to demonstrate awareness and understanding of digital design flow.||design and apply advanced technical methodologies to achieve a design illustrating the principles of digital design flow.|
Your achievement of the learning outcomes for this module will be tested as follows:
|Description||Complete a number of detailed design exercise. The design exercise include a 7 segment BCD display, Gray encoder and the development of the infrastructure required to support an ADC application.|
Before taking this module you must have successfully completed the following:
No restrictions apply.
Smith M.J. Application-Specific Integrated Circuits, Addison Wesley, 1997, ISBN 0-201-50022-1
Palnitkar Samir, Verilog HDL, A guide to Digital Design and Synthesis, Prentice Hall, 1996 ISBN 0-134-51675-3
Weste N.H.E. and Eshraghian K, Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley ISBN 0-201-53376-6
De Micheli, G. Synthesis and Optimisation of Digital Circuits, McGraw Hill, 1994, ISBN 0-070-16333-2
A. Vladimirescu, The SPICE Book, John Wiley & Sons, 1994, ISBN 0-471-60926-9
A. Rushton, VHDL for Logic Synthesis, 2nd edition, J. Wiley, 1998, ISBN 0-471-98325-X
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