15 credits at level HE7
Digital engineers can and do operate with no knowledge of the underlying physical structures and processes utilised. In contrast, it is impossible to be an effective analogue or RF design engineer without a comprehensive understanding of the theoretical device characteristics and the physical aspects and interactions of the structures produced and used on the chip. This includes both the single device and the interactions of multiple devices in a design. Analogue engineers will routinely layout, or provide instructions to layout engineers as part of their normal design process. This is a important part of analogue ASIC design. The devices used, and their structures have a significant impact on the performance of any analogue design. The ability to interpret ASIC design rules and process parameters and understand their impact on physical structures is an important aspect of the analogue engineer’s role.
The module is intended to provide students with the ability to interpret design rules and to be able to produce “good” layouts for various macro classes. The intention is for the students to be able to analyse, implement and layout analogue macros utilising “best practice” techniques for a given process. The module will include aspects of layout design relating to structures, matching, tolerances, thermal and electrical issues, and issues specific to DSM and high frequency design.
Introduction to Layout
Schematic to layout with Virtuoso XL
- standard cell, semi custom and full custom layout
Physical structure of an ASIC
- physical structure
- breakdown of critical layers and purposes
- how this corresponds to design layers
- physical and non physical layers
- physical structures / layers
- issues and differences
How the layers combine
Physical structures of devices and structures required
- general requirements such as wells and taps
Analysis of the AMS 035 design rules
- how this affects design
Layers and process characteristics and variations
Planning a layout structure
Good design practice / hints and tips for laying out your cell
- device orientations and cell structures
- power / IR drops
- thermal issues
- charge and substrate issues
- combining components and their area
- source/drain of transistors
Allowing for change / accommodating change
Drawing the layout
Polygon pushing using a layout editor
- how to use one / how to do it
- salient aspects
- snap, gravity and grids
What structures you can draw
Advanced Layout Issues
- device structures process issues
- reducing the sensitivity to process issues
- why some shapes are good / bad
PCells/ROD and Vias
How they work
Standard cell / leaf cells and structures
Making a layout from a schematic
- designing with PCells
- floorplanning your structure
- some features of Virtuoso XL
Checking the result
- understanding them and how they impact on full custom layout
- design rules checks analysis of the 0.35um rules
- how they work, how you find errors, how you identify and fix errors
- tutorial examples with common and unusual errors correlated with the relevant design rules and explanations
- how we check the schematic against the layout
- extraction decks: how they work
- how the device matching is done; why it needs help
- hierarchical versus flat
- cross probing
- Parasitic extraction
- what it is, why we do it and how we use it.
The intention is to develop the subject using a large number of tutorial layouts and layout/schematics. This will ensure that students gain actual experience of creating the relevant structures, of debugging them and tracking down errors and issues. Some of the errors will have been introduced deliberately, giving students the opportunity to build their own set of “FAQs” when they encounter the errors in their own constructions.
It is intended that all exercises will be based on the AMS 0.35um, 4 layer metal design kit revision 3.60 or 3.70
The module will be taught and assessed entirely by distance learning, students having remote access to suitable software running on the servers at Bolton. Where appropriate, and on request, tutors will make use of the "shadowing" facility to take control of a student's design and instruct the student in real time.
Two assignments are planned. The first assignment will involve the layout design of a relatively simple circuit such as an integer PLL. In the final assignment students will be provided with the schematics and specification of a more complex circuit such as a current steering AtoD. 30% of marks will be allocated to the first assignment and 70% to the second.
The assignments will be designed to provide students with the opportunity to demonstrate their understanding of the techniques and issues covered. To accompany the design they should provide a written analysis of the exercise and the issues and reasoning behind the structures created.
when you have successfully completed this module you will:
to demonstrate that you have achieved the learning outcome you will:
|1.||have an understanding of the structures and principles involved in layout design.
||demonstrate the ability to successfully create layouts using polygon layer editing devices and structures, ensuring that these structures meet the process design rules and pass DRC rules. Modify the devices so they extract correctly to allow LVS checks to be successfully completed for digital and analogue primitive devices.|
|2.||be aware of the practical aspects, including DSM issues and high frequency/RF design.
||Produce layouts for a variety of analogue circuits and thereby demonstrate an understanding of the thermal, electrical and process related issues that need to be considered in the structure, location and choice of components on the layouts. Be able to manipulate and connect devices using the appropriate layers and constructs to produce a final layout that passes all relevant checks and makes "efficient" use of the area used.|
|3.||have gained a basic level of competence in layout design, including an understanding of, and the ability to perform, DRC, ERC and LVS layout checks.||
Using PCells and polygon editors, manually create layouts for analogue circuits. Demonstrate ability to successfully run DRC, ERC and LVS design rule checks, and to be able to interpret, identify and correct issues identified by these operations.
Your achievement of the learning outcomes for this module will be tested as follows:
|Description||Implement the layout of a relatively simple circuit.||Implement the layout of a more complex circuit. Optimise the design to meet a demanding specification, taking note of information derived from design rule checks.|
Before taking this module you must have successfully completed the following:
No restrictions apply.
Dan Clien, CMOS IC Layout - available online via Athens authenticated access from the university.
Weste and Harris CMOS VLSI Design, A Circuits and Systems Perspective
Baker, Li and Boyce CMOS Circuit Design, Layout and Simulation
Conference and Journal Papers
Many will be referenced or recommended when the teaching material is developed.
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